Reliability Characterization for Advanced DRAM using HK/MG + EUV Process Technology
Seoul Lee, G.-J. Kim, N-H. Lee, KW. Lee, B.W. Woo, Jahoon Jin, JG. Kim, YS. Lee, Hyoung Seop Kim, Sangwoo Pae
Abstract
Extensive reliability characterization of advanced DRAM (with and without HK/MG) with EUV process technology is presented. The technology features buried-channel array transistor(BCAT), dual-poly gate core/periphery transistors, 4-metal layers with Cu/Al interconnects, embedded DRAM capacitor, and with 8, 12, 16Gb chips, enabling mobile LPDDRs, Graphic-DDR, HBM, and making up to 128-256GB DIMMs for server applications. FEOL and BEOL WLR reliability demonstrated showed well above 10 yrs, 125°C intrinsic performance and were also validated with long term months of stresses including 1000 hrs ofHTOL and> 6 months package level stresses. DIMMs were also tested with various workloads using server systems, for more than 1 yr, accurately validating the excellent reliability results that showed only few hundred ppms on 32-64GB DIMMs. Early fails can be further optimized by process defect control and test screens, such as burn-in. The DRAM memories are well in volume production.