Enabling static random-access memory cell scaling with monolithic 3D integration of 2D field-effect transistors
Muhtasim Ul Karim Sadaf, Ziheng Chen, Shiva Subbulakshmi Radhakrishnan, Yongwen Sun, Lei Ding, Andrew R. Graves, Yang Yang, Joan M. Redwing, Saptarshi Das
Abstract
Static Random-Access Memory (SRAM) cells are fundamental in computer architecture, serving crucial roles in cache memory, buffers, and registers due to their high-speed performance and low power consumption. However, scaling SRAM cells to advanced technology nodes poses significant challenges. Three-dimensional (3D) integration offers a promising solution for reinstating SRAM scaling by vertically stacking devices, thereby reducing the physical footprint. In this study, we demonstrate approximately 40% reduction in cell area and improved interconnect length for 3D SRAM cells constructed from field-effect transistors (FETs) based on monolayer MoS2, compared to the planar design. Using the layout for the 450 nm technology node, our 2-tier 3D SRAM design achieves better integration density than the planar 350 nm node. Furthermore, we project up to 70% reduction in cell area for 3-tier 3D SRAM cells, closely matching the cell area of the planar 250 nm node. We have successfully realized 1 kilobit of planar SRAM and 2-tier 3D SRAM cell arrays occupying areas of 0.0358 mm² and 0.0251 mm², respectively, each comprising 6144 MoS2 FETs. Finally, we project the footprint advantage for 3D SRAM cells at scaled technology nodes. Our demonstration highlights the potential of 3D integration of 2D FETs in advancing SRAM technology. The downscaling process of conventional static random-access memory (SRAM) cells has recently slowed down, posing challenges for future electronic devices. Here, the authors demonstrate ~40% reduction in cell area and improved interconnect length for 2-tier 3D-integrated SRAM cells based on 2D MoS2 transistors.