PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference
Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo
Abstract
We present a programmable in-memory computing (IMC) accelerator integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We developed a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28nm prototype chip achieves system-level peak energy-efficiency of 437 TOPS/W and peak throughput of 4.9 TOPS at 40MHz, 1V supply.
Topics & Concepts
Computer scienceSIMDStatic random-access memoryThroughputComputer hardwareRegister fileChipMacroCapacitive couplingHardware accelerationTOPSApplication-specific integrated circuitComputer architectureEmbedded systemField-programmable gate arrayParallel computingWirelessElectrical engineeringVoltageEngineeringOperating systemInstruction setProgramming languageMechanical engineeringTelecommunicationsSpinningAdvanced Memory and Neural ComputingFerroelectric and Negative Capacitance DevicesCaching and Content Delivery