An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications

Jixuan Li, Ka-Fai Un, Wei-Han Yu, Pui‐In Mak, Rui P. Martins

2021IEEE Transactions on Circuits & Systems II Express Briefs65 citationsDOI

Abstract

The computational efficiency is the prime concern of a computation-intensive deep convolutional neural network (CNN). In this Brief, we report an FPGA-based computation-efficient reconfigurable CNN accelerator. It innovates in the utilization of a kernel partition technique to substantially reduce the repeated access to the input feature maps and the kernels. As a result, it balances the ability for parallel computing while consuming less system power. Experimental results prove that the proposed CNN accelerator achieves a peak throughput of 220.0 GOP/s with an energy efficiency of 22.9 GOPs/W at 151.4 frames/s for the AlexNet. It is also reconfigurable to process VGG-16 befitting complex object recognition.

Topics & Concepts

Computer scienceConvolutional neural networkField-programmable gate arrayComputationHardware accelerationPartition (number theory)Kernel (algebra)ThroughputEfficient energy useParallel computingProcess (computing)Artificial intelligenceComputer architectureComputer hardwareAlgorithmElectrical engineeringTelecommunicationsCombinatoricsOperating systemWirelessMathematicsEngineeringAdvanced Neural Network ApplicationsCCD and CMOS Imaging SensorsAdvanced Image and Video Retrieval Techniques