Chiplet actuary
Yinxiao Feng, Kaisheng Ma
Abstract
Multi-chip integration is widely recognized as the extension of Moore's Law. Cost-saving is a frequently mentioned advantage, but previous works rarely present quantitative demonstrations on the cost superiority of multi-chip integration over monolithic SoC. In this paper, we build a quantitative cost model and put forward an analytical method for multi-chip systems based on three typical multi-chip integration technologies to analyze the cost benefits from yield improvement, chiplet and package reuse, and heterogeneity. We re-examine the actual cost of multi-chip systems from various perspectives and show how to reduce the total cost of the VLSI system through appropriate multi-chiplet architecture.
Topics & Concepts
ReuseComputer scienceChipActuarySystem on a chipSystem integrationVery-large-scale integrationEmbedded systemComputer architectureReliability engineeringEngineeringTelecommunicationsDatabaseFinanceEconomicsWaste managementVLSI and FPGA Design Techniques3D IC and TSV technologiesVLSI and Analog Circuit Testing