Simple Clock Drift Estimation and Compensation for Packet-Level Index Modulation and Its Implementation in LoRaWAN
Kohei Tsurumi, Aoto Kaburaki, Koichi Adachi, Osamu Takyu, Mai Ohta, Takeo Fujii
Abstract
Low-power wide-area network (LPWAN), which includes the long-range wide-area network (LoRaWAN) protocol, is an enabling technology that satisfy low power consumption and long-range communication. In many applications of LPWAN, an end node (EN) transmits data at regular intervals. Based on this, we had previously proposed the concept of packet-level index modulation (PLIM) to increase the number of information bits transmitted by one data packet. In PLIM, the generation interval between two consecutive packets is split into multiple time slots. Each EN transmits its packet in a specific combination of time slot and frequency channel, which represents the index, to convey additional information bits. To retrieve additional information, the gateway (GW) detects the time slot in which the data packet is being transmitted. Therefore, accurate synchronization between EN and GW is essential. However, clock drift occurs due to the inexpensive real-time clock oscillator on each EN, which results in timing misalignment between each node and the GW. This article proposes a simple clock drift estimation and compensation method for the PLIM. An experimental measurement is performed to model the clock drift. The numerical results obtained using the clock drift model show that it can accurately detect the time slot index under the influence of clock drift. Furthermore, PLIM is implemented on a commercial LoRaWAN node and GW to demonstrate its practicability.