Integer vs. Floating-Point Processing on Modern FPGA Technology
Don Lahiru Nirmal Hettiarachchi, Venkata Salini Priyamvada Davuluru, Eric J. Balster
Abstract
Historically, FPGA designers have used integer processing whenever possible because floating-point processing was prohibitively costly due to higher logic requirements and speed reduction. Therefore, fixed-point processing was the norm. Recently, Intel introduced the Arria 10 FPGA which is the industry's first FPGA that includes single-precision hardened Floating-Point Units (FPUs) on DSP blocks. With the advent of hardened floating-point, FPGA designers have largely abandoned fixed-point processing. This paper introduces a series of arithmetic tests to evaluate whether fixed-point processing is obsolete considering the FPGA performance. A performance metric is developed to calculate the FPGA performance in terms of logic utilization and kernel speed. All programs are tested with Intel Stratix V FPGA which does not have hardened FPUs and Intel Arria 10 FPGA for comparison. The performance metric indicates that, on average, there is a 20.18% performance increase when Stratix V processes fixed-point operations and 27.17% performance increase when Arria 10 processes fixed-point operations. Even with hardened FPUs, it is shown that the Arria 10 FPGA exhibits a significant logic reduction when processing fixed-point operations. The results clearly indicate that the FPGAs perform better when processing converted fixed-point arithmetic operations compared to floating-point arithmetic regardless of whether they include hardened FPUs.