Novel Enhancement-Mode p-Channel GaN MOSFETs With an AlN Insert Layer
Hai Huang, Maolin Pan, Qiang Wang, Xinling Xie, Yannan Yang, Xin Hu, Luyu Wang, Penghao Zhang, Min Xu, David Wei Zhang
Abstract
In this work, an enhancement-mode (E-mode) p-channel GaN metal-oxide-semiconductor field-effect transistor (p-MOSFET) with a maximum ON-state current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {ON}}$ </tex-math></inline-formula>) density of 10.5 mA/mm, threshold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula>) of −2.45 V, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {ON}}/{I}_{\text {OFF}}$ </tex-math></inline-formula> ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{8}}$ </tex-math></inline-formula> is demonstrated on a commercial GaN wafer designed on a p-GaN HEMT. Furthermore, we present a novel E-mode p-FET featuring an AlN insertion layer within the p-GaN layer. The AlN layer introduces extra capacitance in the conducting channel and decreases the body factor m of devices. The p-GaN/AlN/p-GaN/AlGaN structure reduces the equivalent channel capacitance, achieving a minimum point-by-point subthreshold swing (SS) of 60 mV/dec. Compared with that of the conventional p-GaN channel FET, the SS decreases from 225 to 105 mV/dec over three orders, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shifts to −3.05 V, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {ON}}/{I}_{\text {OFF}}$ </tex-math></inline-formula> ratio increases to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2 \times 10^{{8}}$ </tex-math></inline-formula>, and the device also has an ultralow off-state leakage current in the range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10 \; ^{-{8}}$ </tex-math></inline-formula> mA/mm. The proposed structure is compelling for GaN-based complementary metal-oxide-semiconductor (CMOS) logic and power devices.