Litcius/Paper detail

ScaleHLS

Hanchen Ye, Hyegang Jun, Hyunmin Jeong, Stephen Neuendorffer, Deming Chen

2022Proceedings of the 59th ACM/IEEE Design Automation Conference41 citationsDOI

Abstract

This paper presents an enhanced version of a scalable HLS (High-Level Synthesis) framework named ScaleHLS, which can compile HLS C/C++ programs and PyTorch models to highly-efficient and synthesizable C++ designs. The original version of ScaleHLS achieved significant speedup on both C/C++ kernels and PyTorch models [14]. In this paper, we first highlight the key features of ScaleHLS on tackling the challenges present in the representation, optimization, and exploration of large-scale HLS designs. To further improve the scalability of ScaleHLS, we then propose an enhanced HLS transform and analysis library supported in both C++ and Python, and a new design space exploration algorithm to handle HLS designs with hierarchical structures more effectively. Comparing to the original ScaleHLS, our enhanced version improves the speedup by up to 60.9× on FPGAs. ScaleHLS is fully open-sourced at https://github.com/hanchenye/scalehls.

Topics & Concepts

SpeedupComputer scienceScalabilityDesign space explorationCompilerParallel computingComputer architecturePython (programming language)Field-programmable gate arrayHigh-level synthesisKey (lock)Programming languageComputer engineeringEmbedded systemOperating systemParallel Computing and Optimization TechniquesEmbedded Systems Design TechniquesCloud Computing and Resource Management
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