7.6 A High-Speed Back-Illuminated Stacked CMOS Image Sensor with Column-Parallel kT/C-Cancelling S&H and Delta-Sigma ADC
Chihiro Okada, Koushi Uemura, Luong Dinh Hung, Kouji Matsuura, Takashi Moue, Daisuke Yamazaki, Kazutoshi Kodama, Masafumi Okano, Takafumi Morikawa, Kazuyoshi Yamashita, Osamu Oka, Itai Shvartz, Golan Zeituni, Ariel Benshem, Noam Eshel, Yoshiaki Inada
Abstract
In recent years, there has been growing demand for high-resolution and large-format CMOS image sensors in Digital Still Camera, Security, and Factory Automation uses. In addition, new uses such as airborne mapping [1] are now being reported. Focusing on the camera market, there is currently demand for simultaneously realizing high image quality, high frame rate, and low power consumption, all within a larger-than-APS-C format. For most cases, the single-slope ADC (SS ADC) [2] architecture is used in commercialized CMOS image sensors. In order to accelerate frame rate, the counting-clock frequency can be increased up to 2.376GHz as demonstrated in [3], but maintaining clock waveform quality without increasing power is a major challenge for low-power operation. Adaptive gain operation using a dual gain amplifier is reported in [4], but SS ADCs based on adaptive gain operation still have frame rate issues from increasing bit resolution, e.g., to 14b.