Differentiable-timing-driven global placement

Zizheng Guo, Yibo Lin

2022Proceedings of the 59th ACM/IEEE Design Automation Conference40 citationsDOI

Abstract

Placement is critical to the timing closure of the very-large-scale integrated (VLSI) circuit design flow. This paper proposes a differentiable-timing-driven global placement framework inspired by deep neural networks. By establishing the analogy between static timing analysis and neural network propagation, we propose a differentiable timing objective for placement to explicitly optimize timing metrics such as total negative slack (TNS) and worst negative slack (WNS). The framework can achieve at most 32.7% and 59.1% improvements on WNS and TNS respectively compared with the state-of-the-art timing-driven placer, and achieve 1.80× speed-up when both running on GPU.

Topics & Concepts

Computer sciencePlacementDifferentiable functionVery-large-scale integrationStatic timing analysisArtificial neural networkClosure (psychology)Parallel computingComputer engineeringComputer architectureAlgorithmReal-time computingEmbedded systemCircuit designPhysical designArtificial intelligenceMathematicsEconomicsMathematical analysisMarket economyVLSI and FPGA Design TechniquesVLSI and Analog Circuit TestingLow-power high-performance VLSI design