An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network
Sunghoon Kim, Wonjae Lee, Sundo Kim, Sungjin Park, Dongsuk Jeon
Abstract
In-Memory Computing (IMC) has been widely studied to mitigate data transfer bottlenecks in von Neumann architectures. Recently proposed IMC circuit topologies dramatically reduce data transfer requirements by performing various operations such as Multiply-Accumulate (MAC) inside the memory. In this paper, we present an SRAM macro designed for accelerating Memory-Augmented Neural Network (MANN). We first propose algorithmic optimizations for a few-shot learning algorithm employing MANN for efficient hardware implementation. Then, we present an SRAM macro that efficiently accelerates the algorithm by realizing key operations such as L1 distance calculation and Winner-Take-All (WTA) operation through mixed-signal computation circuits. Fabricated in 40nm LP CMOS technology, the design demonstrates 27.7 TOPS/W maximum energy efficiency, while achieving 93.40% and 98.28% classification accuracy for 5-way 1-shot and 5-way 5-shot learning on the Omniglot dataset, which closely matches the accuracy of the baseline algorithm.