DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications
Suresh Nambi, Uppugunduru Anil Kumar, Kavya Radhakrishnan, Mythreye Venkatesan, Syed Ershad Ahmed
Abstract
Approximate computing is a promising method for designing power-efficient computing systems. Many image and compression algorithms are inherently error-tolerant and can allow errors up to a specific limit. In such algorithms, savings in power can be achieved by approximating the data path units, such as a multiplier. This letter presents a novel decoder logic-based multiplier design with the intent to reduce the partial products generated. Thus, leading to a reduction in the hardware complexity and power consumption while maintaining a low error rate. Our proposed design in an 8-bit format which achieves 40.96% and 22.30% power reduction compared to the accurate and approximate multipliers. Comprehensive simulations are carried out on image sharpening and compression algorithms to prove that the proposed design obtains a better quality-effort tradeoff than the existing multipliers.