A Power-Efficient Bridge Readout Circuit for Implantable, Wearable, and IoT Applications
Ahmad Rezvanitabar, Gwangrok Jung, Yusuf S. Yaras, F. Levent Degertekin, Maysam Ghovanloo
Abstract
A power-efficient bridge-to-digital sensing interface is proposed, which also offers immunity against power supply noise. The interface utilizes duty-cycling to reduce the static power consumption of resistive bridge sensors, which are commonly used in implantable, wearable, and internet of things (IoT) applications, such as intracranial pressure (ICP) sensing and blood pressure (BP) monitoring. The proposed interface uses a revised version of the pseudo-pseudo differential (PPD) topology with the ping-pong technique to reduce the complexity of traditional fully-differential counterparts. A proof-of-concept prototype has been fabricated in 0.35-μm CMOS and occupies an active area of 0.48 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It achieves 9.13 effective number of bits (ENOB) at 3.72 kHz sampling rate and improvement of more than 50 dB in the power supply rejection ratio (PSRR) by employing the ping-pong technique. It reduces the power consumption of a 5-kΩ Wheatstone bridge by 99.6% compared to a traditional interface, down to 2.53 μw at 1.8 V supply. The functionality of the system has also been demonstrated in an experimental setup in conjunction with an embedded resistive bridge pressure sensor.