FPGA Implementation Framework for Low Latency Nonlinear Model Predictive Control
Vaishali Patne, Deepak Ingole, Dayaram Sonawane
Abstract
Embedded implementation of real-time Nonlinear Model Predictive Control (NMPC) is extremely challenging and complex. This paper presents a framework for implementation of NMPC on Field Programmable Gate Array (FPGA). We show the step-by-step procedure of FPGA implementation framework design of NMPC for a case study of 2D-crane system. In the implementation, we used GRAMPC software to construct NMPC and subsequently generate an FPGA specific low-level C/C++ code of the optimization solver. Generated C/C++ code is optimized for memory, speed, and resource utilization by the customized approach of applying pipelining and directives using Xilinx Vivado HLS toolchain. The NMPC is implemented on a Xilinx’s ZYNQ-7000 SoC ZC706 FPGA board. The detailed analysis of the controller computational complexity in terms of memory, resource utilization, clock, and power consumption is presented. The performance of implemented NMPC is verified through Hardware-in-the-Loop (HIL) co-simulation using system generator tool. The presented results show the feasibility of FPGA-based GRAMPC framework for ultra-fast applications of NMPC.