CMOS-Memristor Hybrid Design of A Neuromorphic Crossbar Array with Integrated Inference and Training
Sarah Johari, Arghavan Mohammadhassani, M. Lakshmi Varshika, Anup Das
Abstract
We present a CMOS-Memristor hybrid analog design of a neuromorphic crossbar array with integrated inference and training. Each crosspoint on the crossbar includes a memristor to store synaptic weights. Integrate-and-fire (IF) neurons are designed using CMOS transistors and placed along the rows and columns of the crossbar. Learning of synaptic weights is facilitated using the trace-driven spike timing-dependent plasticity (TrSTDP) rule, where the trace (i.e., difference in spike timings) collected during forward propagation (i.e., inference) is used to compute weight updates. The key novelty of our design is an interface circuit that captures the trace during inference and autonomously controls the learning circuit (designed using memristor) to generate the appropriate voltage pulse width necessary to update the synaptic weight, without requiring any software/system support. Our interface circuit consists of a voltage-to-time converter (VTC), adder, and a voltage amplifier, all of which are designed using CMOS transistors. We implement the proposed design using Synopsys HSPICE at 90nm technology node and thoroughly evaluate the accuracy, latency, area, and power overheads of the interface circuit.