2.3D Hybrid Substrate with Ajinomoto Build-Up Film for Heterogeneous Integration
Gary Chang-Fu Chen, John H. Lau, Channing Cheng-Lin Yang, Jones Yu-Cheng Huang, Andy Yan-Jia Peng, Hsing-Ning Liu, Tzyy-Jang Tseng, Ming Li
Abstract
fan-out chip-last panel-level packaging for heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, fabrication and reliability of: (a) the heterogeneous integration of one large chip and one small chip with 50μm-pitch (minimum), (b) a fine metal linewidth and spacing redistribution-layer substrate on a temporary glass carrier, (c) an ordinary build-up package substrate on a panel, (d) a hybrid substrate which is by soldering the redistribution-layer substrate on top of the build-up substrate, and (e) the chips to hybrid substrate bonding and underfilling. The dielectric material for the redistribution-layer substrate is an Ajinomoto build-up film. The design and analysis of the heterogeneous integration of the two-chip package on the hybrid substrate are performed by a nonlinear temperature- and time-dependent finite-element method.