A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application
Yan Li, Xu Cheng, Chiyu Tan, Jun Han, Yuanfu Zhao, Liang Wang, Tongde Li, Mehdi B. Tahoori, Xiaoyang Zeng
Abstract
Soft errors induced by high energy particles have been a severe concern in integrated circuits. Especially in advanced nanoscale technology nodes, the phenomenon of multinode-upset caused by charge sharing is becoming a crucial issue. However, this problem remains a challenge as there are only few mitigation methods. This brief demonstrates a cost-efficient latch named CROUT featuring double-node-upset tolerance. Integrating coupled Schmitt-triggers and four always-on high-threshold transistors, CROUT is highly reliable in the presence of double-node-upset. To further validate this, a test chip was fabricated in the 28nm CMOS process and tested in a heavy-ion radiation environment. The experimental results indicated that the radiation tolerance is about 2× higher than the standard latches. Moreover, compared to other state-of-the-art multi-nodeupset tolerant latches, its power-delay-product (PDP) is reduced by ~6×. The results show that our proposed latch is highly reliable and cost-effective for the space application, which further can be made into a standard cell to be integrated into large-scale circuits.