Cradle-to-gate Life Cycle Assessment of CMOS Logic Technologies
Lizzie Boakes, M. Garcia Bardon, Vincent Schellekens, I.-Y. Liu, Benjamin Vanhouche, Gioele Mirabelli, Farid Sebaai, L. Van Winckel, Emily Gallagher, Cédric Rolin, L.-Å. Ragnarsson
Abstract
While concerted efforts have been made to promote greener IC manufacturing, achieving sustainable practices necessitates a comprehensive understanding of the environmental impacts associated with semiconductor fabrication. This paper presents a life cycle analysis of logic technology nodes N28 to A14 based on bottom-up modeling of a high-volume IC fabrication plant. This holistic approach provides granular results, enables sensitivity analysis, and highlights high-impact processes that could be improved to reduce environmental footprints in existing and pathfinding technologies.