A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion
Xiangxing Yang, Nan Sun
Abstract
This work proposes a charge-domain 4-bit multiply-and-accumulate (MAC) macro for deep neural network (DNN) accelerators. The proposed macro requires only 1 analog to digital converter (ADC) operation for the entire 512 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 4 b MAC. The one-shot conversion is achieved by sampling partial MAC products onto properly sized capacitors in the SAR ADC. As a result, all MAC operations are finished in the charge domain by the end of ADC sampling, allowing only 1 analog-to-digital (A/D) conversion per multi-bit MAC. To further reduce energy consumption, the SAR ADC features bypass window-based conversion skipping and embedded rectified linear unit (ReLU) activation. The prototype is fabricated in 65-nm complementary metal-oxide semiconductor (CMOS) process with an active area of 0.18 mm2. The measured throughput is 56.3 giga operations per second (GOPS) with 345.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power consumption, achieving 164 tera operations per watt (TOPS/W) energy efficiency.