Mitigating Gate Oscillations of Parallel SiC MOSFETs for Enhanced Performance in DC Solid-State Circuit Breaker
Xin Wu, Yifei Wu, Yi Wu, Mingzhe Rong, Chuangchuang Tao, Yu Xiao, Jingshuai Wang
Abstract
Solid-state circuit breaker (SSCB) is emerging as a new solution for DC distribution network fault protection due to its ultra-fast operation speed and long lifetime. Silicon-carbide-based metal-oxide-semiconductor field effect transistors (SiC MOSFETs) are ideal devices for solid-state circuit breakers due to their low on-state loss. Currently available SiC MOSFET devices fall short of meeting the demands for high-current interruption and SiC MOSFETs often need to be used in parallel. However, effective solutions for mitigating the issue of gate oscillations in parallel SiC MOSFETs, particularly during current breaking applications, are lacking. This paper introduces a low-inductance and symmetrical direct bonded copper (DBC) layout to mitigate gate oscillations of parallel SiC MOSFETs in SSCBs. Theoretical analysis establishes that asymmetric circuit layout leads to gate oscillations, with source parasitic inductance emerging as the dominant factor. The proposed circular DBC layout significantly enhances the symmetry of the parallel circuit, with a mere 2.6 nH loop parasitic inductance. As an auxiliary approach, the design of gate drive circuit and snubber circuit are also discussed. Successful 1 kA current breaking tests of ± 375 V SSCB prototype proved the scientific validity of the proposed solution.