Self-rectifying resistance switching memory based on a dynamic p–n junction
Changjin Wu, Xiaoli Li, Xiaohong Xu, Bo Wha Lee, Seung Chul Chae, Chunli Liu
Abstract
Abstract Although resistance random access memory (RRAM) is considered as one of the most promising next-generation memories, the sneak-path issue is still challenging for the realization of high-density crossbar memory array. The integration of the rectifying effect with resistance switching has been considered feasible to suppress the sneaking current. Herein, we report a self-rectifying resistance switching (SR-RS) by a newly discovered Li ions migration induced dynamic p–n junction at the Li-doped ZnO and ZnO layer interface. The Au/Li–ZnO/ZnO/Pt structure exhibits a forming-free and stable resistance switching with a high resistance ratio of R OFF / R ON ∼ 10 4 and a large rectification ratio ∼10 6 . In the Li–ZnO/ZnO bilayer, the electric field drives the dissociation and recombination of the self-compensated <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:mi mathvariant="normal">L</mml:mi> <mml:msubsup> <mml:mrow> <mml:mi mathvariant="normal">i</mml:mi> </mml:mrow> <mml:mrow> <mml:mi mathvariant="normal">Z</mml:mi> <mml:mi mathvariant="normal">n</mml:mi> </mml:mrow> <mml:mrow> <mml:mo>−</mml:mo> </mml:mrow> </mml:msubsup> <mml:mo>−</mml:mo> <mml:mi mathvariant="normal">L</mml:mi> <mml:msubsup> <mml:mrow> <mml:mi mathvariant="normal">i</mml:mi> </mml:mrow> <mml:mrow> <mml:mi mathvariant="normal">i</mml:mi> </mml:mrow> <mml:mrow> <mml:mo>+</mml:mo> </mml:mrow> </mml:msubsup> </mml:math> complex pairs ( <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:mi mathvariant="normal">L</mml:mi> <mml:msubsup> <mml:mrow> <mml:mi mathvariant="normal">i</mml:mi> </mml:mrow> <mml:mrow> <mml:mi mathvariant="normal">Z</mml:mi> <mml:mi mathvariant="normal">n</mml:mi> </mml:mrow> <mml:mrow> <mml:mo>−</mml:mo> </mml:mrow> </mml:msubsup> <mml:mo>:</mml:mo> </mml:math> p-type substitutional defect; <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:mi mathvariant="normal">L</mml:mi> <mml:msubsup> <mml:mrow> <mml:mi mathvariant="normal">i</mml:mi> </mml:mrow> <mml:mrow> <mml:mi mathvariant="normal">i</mml:mi> </mml:mrow> <mml:mrow> <mml:mo>+</mml:mo> </mml:mrow> </mml:msubsup> <mml:mo>:</mml:mo> </mml:math> n-type interstitial defect) through the transport of <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:mi mathvariant="normal">L</mml:mi> <mml:msubsup> <mml:mrow> <mml:mi mathvariant="normal">i</mml:mi> </mml:mrow> <mml:mrow> <mml:mi mathvariant="normal">i</mml:mi> </mml:mrow> <mml:mrow> <mml:mo>+</mml:mo> </mml:mrow> </mml:msubsup> </mml:math> between the two layers, thereby induces the formation of a dynamic p–n junction. Using this structure as a memory stacking device, the maximum crossbar array size has been calculated to be ∼16 Mbit in the worst-case scenario, which confirms the potential of the proposed device structure for the selection-device free and high-density resistance random access memory applications.