A Picowatt CMOS Voltage Reference Operating at 0.5-V Power Supply With Process and Temperature Compensation for Low-Power IoT Systems
Jing Wang, Xuan Sun, Lin Cheng
Abstract
This brief presents a picowatt PVT-insensitive CMOS voltage reference with ultra-low supply voltage. The core circuit of the proposed reference consists of three subthreshold-biased PMOS transistors, and process and temperature compensation are achieved by employing the width-induced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ th}}$ </tex-math></inline-formula> modulation and self-body-biasing techniques. The reference was implemented in a standard 180-nm CMOS process. With a power supply of 0.5 V at 25 °C, the measurement results of 16 chips show a mean reference voltage of 288 mV with a standard deviation of 1.65 mV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(\sigma /\mu \,\,=$ </tex-math></inline-formula> 0.57%). The line sensitivity is 0.23%/V with a minimum supply voltage of 0.5 V. The average temperature coefficient is 90 ppm/°C after batch trimming over a temperature range of −10°C to 100°C. The power consumption at room temperature is 500 pW, and the active area is 0.0029 mm2.