Panel-Level Fan-Out RDL-First Packaging for Heterogeneous Integration
John H. Lau, Cheng-Ta Ko, Kai-Ming Yang, Chia-Yu Peng, Tim Xia, Puru Bruce Lin, Jiahe Chen, Patrick Po-Chun Huang, Hsing-Ning Liu, Tzyy-Jang Tseng, Eagle Lin, Leo Chang
Abstract
In this article, the fan-out chip-last panel-level packaging for heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, fabrication, and simulation of thermomechanical reliability of a heterogeneous integration of one large chip (10 mm × 10 mm) and two small chips (7 mm × 5 mm) by a fan-out method with a redistribution-layer (RDL)-first substrate fabricated on a 515 mm × 510 mm panel. Reliability assessment by thermomechanical simulation includes thermal cycling of the heterogeneous integration of the three-chip package on a printed circuit board (PCB) assembly that is performed by a nonlinear temperature- and time-dependent finite-element simulation.