A Study on Memory Stack Process by Hybrid Copper Bonding (HCB) Technology
Sanghoon Lee, Youngkun Jee, Sangcheon Park, Soo-Hwan Lee, Bohee Hwang, Gyeongjae Jo, Chungsun Lee, Jumyong Park, Aeni Jang, Hyunchul Jung, Il-Hwan Kim, Dongwoo Kang, Seungduk Baek, Dae Woo Kim, Unbyung Kang
Abstract
Hybrid copper bonding (HCB) technology has been introduced and evaluated to overcome a fine pitch limit and degradation in thermal properties in 3D semiconductor package structure. In this study, we successfully demonstrated 3D memory stacking package by HCB technology which integrated Cu-Cu diffusion bonding along with oxide bonding simultaneously. HCB process was developed and die-to-wafer (D2W) multi-stack structure was realized which shows excellent electrical and thermal properties. The flatness of the bonding surface was controlled by chemical mechanical polishing (CMP), and highly activated bonding surface desirable for HCB was obtained through optimization of plasma condition. The properties of the chip surface were measured in terms of oxide topography, Cu dishing height, surface hydrophilicity, hydroxyl group density, and adhesion force. Then package chips were stacked up to 12 levels by HCB method to demonstrate 12 stacked D2W package. In particular, we focused on eliminating oxide voids at the bonding interface since even a single void can deteriorate the functional properties of the whole stacked package. Oxide voids were classified into several categories on the basis of the causes, then the sources of the void were eliminated in advance to achieve void free HCB interfaces. Through the accomplishment of D2W HCB technology, it is expected to be applied to advanced 2.5D/3D packages for superior thermal and electrical performances.