Design of Accelerometers-Based PUF for Internet of Things Security
Wenbo Zhang, Shanshan Wang, Pengjun Wang, Qiang Fu, Xiangyu Li
Abstract
The widespread adoption of high-precision integrated accelerometers with digital output functionality is evident across both military and civilian applications. This research focuses on the application-specific integrated circuit (ASIC) designed for integrated accelerometers, which employs a switched-capacitor topology. The proposed ASIC exhibits key advantages, including a high signal-to-noise ratio (SNR), broad bandwidth, and exceptional linearity. However, integrated accelerometers face significant information security challenges, particularly in Internet of Things (IoT) applications. To address this issue, this work presents a novel ASIC specifically designed to enhance security by enabling the generation of physically unclonable functions (PUFs) within integrated accelerometers. A unique methodology is introduced to derive PUF responses from digital integrated accelerometers by leveraging their inherent manufacturing variations. These intrinsic process variations provide naturally distinct and highly secure cryptographic keys that are challenging to replicate. The feasibility of this approach is validated through comprehensive simulations and experimental measurements on fabricated chips, demonstrating its effectiveness in secure key generation.