Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window
Zhouhang Jiang, Yi Xiao, Swetaki Chatterjee, Halid Mulaosmanovic, Stefan Duenkel, Steven Soss, Sven Beyer, Rajiv Joshi, Yogesh Singh Chauhan, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni
Abstract
In this work, we applied the asymmetric double-gate concept to decouple the tradeoff between ferroelectric (FE) thickness (t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</inf> ) scaling and memory window (MW) reduction in ferroelectric FET (FeFET). We demonstrate that: i) separating read and write gates and adopting a thick non-FE dielectric gate used for reading can amplify the read MW due to electrostatic coupling between the two gates; ii) a compact model for double-gate FeFET has been demonstrated and calibrated with the experimentally measured switching dynamics; iii) with the calibrated model, design space for a scaled t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</inf> (3nm) and logic-compatible write voltage (1.8V) is identified, offering a possible option for t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</inf> scaling.