A 35.5-127.2 TOPS/W Dynamic Sparsity-Aware Reconfigurable-Precision Compute-in-Memory SRAM Macro for Machine Learning
Mustafa Ali, Indranil Chakraborty, Utkarsh Saxena, Amogh Agrawal, Aayush Ankit, Kaushik Roy
Abstract
This letter presents an energy-efficient sparsity-aware reconfigurable-precision compute-in-memory (CIM) 8T-SRAM macro for machine learning (ML) applications. The proposed macro dynamically leverages workload sparsity by reconfiguring the output precision in the peripheral circuitry without degrading application accuracy. Specifically, we propose a new energy-efficient reconfigurable-precision SAR ADC design with the ability to form ( n+m)-bit precision using n-bit and m-bit ADCs. Additionally, the transimpedance amplifier (TIA) “required to convert the summed current into voltage before conversion” is reconfigured based on sparsity to improve sense margin at lower output precision. The proposed macro, fabricated in 65-nm technology, provides 35.5-127.2 TOPS/W as the ADC precision varies from 6 to 2 bit, respectively.