23.1 A 7.9fJ/Conversion-Step and 37.12aF<sub>rms</sub> Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting
Jihang Gao, Linxiao Shen, Heyi Li, Siyuan Ye, Jie Li, Xinhang Xu, Jiajia Cui, Yunhung Gao, Ru Huang, Le Ye
Abstract
In IoT sensor applications, capacitive sensors are widely used to convert various capacitances into digital signals, and the demand for power-efficient high-resolution capacitance-to-digital converters (CDCs) is on the rise. In a high-resolution CDC, kT/C noise, due to the sampling process, becomes dominant in discrete-time systems [1–3], especially in the sub-fF sensor fields. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta \Sigma$</tex> architectures averaging kT/C noise with a high oversampling rate require extended conversion time (~ms) and degraded power efficiency (~pJ/conv.step). The CT <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma$</tex> CDC implemented in [4] eliminates the sampling-induced kT/C noise, but it loses frequency scalability and relies heavily on static high-gain analog components.