Litcius/Paper detail

RTL-MP

Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang

202220 citationsDOIOpen Access PDF

Abstract

In a typical RTL-­to-­GDSII flow, floorplanning plays an essential role in achieving decent quality of results (QoR). A good floorplan typically requires interaction between the frontend designer, who is responsible for the functionality of the RTL, and the backend physical design engineer. The increasing complexity of macro-­dominated designs (especially machine learning accelerators with autogenerated RTL) has made the floorplanning task even more challenging and time­-consuming. In this paper, we propose RTL-­MP, a novel macro placer which utilizes RTL information and tries to "mimic" the interaction between the frontend RTL designer and the backend physical design engineer to produce human-­quality floorplans. By exploiting the logical hierarchy and processing logical modules based on connection signatures, RTL-­MP can capture the dataflow inherent in the RTL and use the dataflow information to guide macro placement. We also apply autotuning to optimize hyperparameter settings based on input designs. We have built RTL­-MP based on OpenROAD infrastructure and applied RTL-­MP to a set of industrial designs. RTL­-MP outperforms state-­of-­the­-art commercial macro placers and achieves QoR similar to that of handcrafted floorplans.

Topics & Concepts

FloorplanDataflowComputer scienceMacroComputer architecturePhysical designElectronic design automationLogic synthesisQuality (philosophy)Parallel computingEmbedded systemProgramming languageCircuit designLogic gateAlgorithmEpistemologyPhilosophyVLSI and FPGA Design TechniquesVLSI and Analog Circuit TestingEmbedded Systems Design Techniques
RTL-MP | Litcius