10 kV, 250°C Operational, Enhancement-Mode Ga<sub>2</sub>O<sub>3</sub> JFET with Charge-Balance and Hybrid-Drain Designs
Yuan Qin, Zineng Yang, Hehe Gong, Alan G. Jacobs, Joseph Spencer, Matthew Porter, Bixuan Wang, Kohei Sasaki, Chia-Hung Lin, Marko J. Tadjer, Yuhao Zhang
Abstract
We report the first 10 kV Enhancement-mode (E-mode) transistor in ultra-wide bandgap (UWBG) materials. This lateral Ga<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> junction-gate field-effect-transistor (JFET) deploys a highly-doped p-type NiO for E-mode gate, as well as the lowly-doped NiO superjunction and hybrid-drain structures for electric field management. The Ga<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> channel is optimized with a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.5\times 10^{18}\text{cm}^{-3}$</tex> doping and two thickness designs of 50 and 160 nm. At 25°C, both JFETs achieve the E-mode and > 10 kV breakdown voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(BV)$</tex>, with the specific on-resistance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(R_{\text{ON},\text{SP}})$</tex> being 92 and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$703\ \mathrm{m}\Omega\cdot \text{cm}^{2}$</tex> for the thick-and thin-channel designs, respectively. At 250°C, the thin-channel JFET remains E-mode with a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$BV$</tex> over 10 kV at zero gate-source bias <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{\text{GS}})$</tex>. In contrast, the thick-channel JFET turns into depletion-mode (D-mode) at high temperatures <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(T)$</tex> and maintains 10 kV <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$BV$</tex> only up to 150°C, due to the insufficient gate control to counter the drain-induced barrier lowering (DIBL) effect. This implies a trade-off between <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\text{ON},\text{SP}}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{high}-T$</tex> stability. Both devices survive the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{high}-T$</tex> gate bias (HTGB) and 3 kV <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{high}-T$</tex> reverse bias (HTRB) reliability tests. Overall, our device presents not only the best figure-of-merits (FOMs) in all >3 kV UWBG transistors, but also the first 250°C operation and 3 kV reliability data in all high-voltage transistors beyond Si and SiC. The unveiled device physics and trade-off can also guide the development of future high-voltage, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{high}-T$</tex> power transistors.