3D Vertical Self-Rectifying Memristor Arrays With Split-Cell Structure, Large Nonlinearity (>10<sup>4</sup>) and fJ-Level Switching Energy
Sheng‐Guang Ren, Yi-Bai Xue, Yu Zhang, Yi Li, Xiangshui Miao
Abstract
High-performance self-rectifying memristor (SRM)-based three-dimensional (3D) architecture with high integration density is an ideal hardware platform for 3D in- memory computing (IMC). In this work, we fabricated Pt/HfO2/TaO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{X}$ </tex-math></inline-formula> /Ta SRM-based 2-layer <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times16$ </tex-math></inline-formula> vertical stacked 3D memristor arrays with split-cell structure. The specially designed structure of the 3D memristor array doubles the integration density of the traditional vertical-stacked resistive random access memory (V-RRAM) and further reduces the bit cost. The SRMs in the 3D memristor arrays show high uniformity, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{4}}$ </tex-math></inline-formula> nonlinearity, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{4}}$ </tex-math></inline-formula> rectification ratio. The SRMs can be fast operated repeatedly at Set (4.5 V/200 ns) and Reset (−2 V/100 ns) pulses for more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{5}}$ </tex-math></inline-formula> cycles resulting in the <30 fJ switching energy. Excellent device-to-device uniformity verifies the high reliability and stability of our fabrication processes. Based on the measured data, we evaluate that, on the premise of 10% read margin, the maximum array size can reach 1.56 Gbit. Our work advances the development of 3D integration and even 3D IMC.