Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance
M. Kobrinsky, J. D Silva, Ehren Mannebach, Sara Mills, M. Abd El Qader, Oladimeji Adebayo, N. Arkali Radhakrishna, M. R. Beasley, J. S. Chawla, Sunny Chugh, Avirup Dasgupta, Urvi Desai, E. De Re, G. Dewey, Terry C. Edwards, C. Engel, Valur Gudmundsson, J. Hicks, B. Krist, R. Mehandru, Inanc Meric, P. Morrow, Debashis Nandi, Pramod Kumar Patel, R. Ramamurthy, Debabrata Samanta, Larry I. Shoer, A. St. Amour, L. H. Tan, Sukru Yemenicioglu, X. Wang, T. Ghani
Abstract
PowerVia increases the efficiency of power delivery by adding back-side interconnects [1]. It also improves performance by relaxing the minimum front-side interconnect pitch and by optimizing them for signaling. Research to further improve performance and density synergistically with PowerVia includes back-side device contacts and device stacking. In this paper, we present an experimental demonstration of a novel cell architecture with back-side device contacts and back side power delivery. Keywords: back-side power delivery, back-side contacts, BSCON.