4.6 A 144Kb Annealing System Composed of 9×16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems
Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Masato Hayashi, Masafumi Tada, Hiroaki Saito, Mayumi Mashimo, Masanao Yamaoka
Abstract
Substantial progress has been made on a new computer architecture, known as an annealing processor (AP) [1-4]. The AP can effectively solve NP-hard combinatorial optimization problems by providing a fast method for finding the grand state of an Ising model. In particular, various types of APs based on a CMOS process (CMOS-AP) significantly improve the scalability and power efficiency of the annealing system by utilizing fast parallel spin updates on the basis of simulated annealing (SA) [2-4]. Further development of CMOS-APs requires overcoming two challenges: improving the accuracy of the annealing processing by expanding the bitwidth of coefficients and attaining a multi-chip annealing system consisting of AP chips with 8-way connectivity. In this work, we developed a scalable CMOS-AP with two key technologies: (i) A flip-flop (FF)-based spin circuit allowing expandable bitwidth by reproducing the Metropolis algorithm, which is SA with a fixed temperature, and (ii) an inter-chip interface (I/F) with a data-compression method utilizing annealing characteristics to obtain multi-chip operation without degrading annealing speed and accuracy. The CMOS-AP demonstrated multichip operation of the 9×16k spin system with an annealing speed 233× faster and a calculation energy 972× lower than running SG3 on a CPU.