Structural Engineering of H<sub>0.5</sub>Z<sub>0.5</sub>O<sub>2</sub>‐Based Ferroelectric Tunneling Junction for Fast‐Speed and Low‐Power Artificial Synapses
Yuanyuan Cao, Yilun Liu, Yafen Yang, Qingxuan Li, Tianbao Zhang, Ji Li, Hao Zhu, Lin Chen, Qingqing Sun, David Wei Zhang
Abstract
Abstract Advanced synaptic devices capable of neuromorphic data processing are widely studied as the building block in the next‐generation computing architecture for artificial intelligence applications. Due to its fast speed, low power, and excellent complementary metal‐oxide‐semiconductor (CMOS) compatibility, Zr‐doped HfO 2 (HZO)‐based ferroelectric tunnel junction (FTJ) are promising candidates as a new type of non‐volatile memory for neuromorphic device applications. Here, an experimental approach is reported to enhance the tunneling efficiency and the electrical performance by engineering the dielectric stack of the FTJ device. By sandwiching the HZO ferroelectric layer with ZrO 2 and Al 2 O 3 layers, the FTJ tunneling current is greatly increased with lowered barrier, larger remnant polarization (P r ), and tunneling electrical resistance ratio as well as suppressed leakage current have been achieved. The optimized FTJ devices are further implemented emulating synaptic functions with demonstrated short/long‐term synaptic plasticity and spike‐timing‐dependent plasticity behaviors. Such engineering in HZO‐based FTJ devices can be promising and instructive for the realization of future ultra‐low‐power and CMOS‐compatible neuromorphic devices and systems.