New Insights into the Interface Trap Generation during Hot Carrier Degradation: Impacts of Full-band Electronic Resonance, (100) vs (110), and nMOS vs pMOS
Zirui Wang, Haoran Lu, Zixuan Sun, Cong Shen, Baokang Peng, Wenfeng Li, Yongkang Xue, Da Wang, Zhigang Ji, Lining Zhang, Yue‐Yang Liu, Xiangwei Jiang, Runsheng Wang, Ru Huang
Abstract
In this paper, the underlying physics of interface trap generation in CMOS devices are revealed, by using full-band distribution of H atom electronic resonance states in Si-H bond at Si/SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> interface, instead of previously assumed single resonance level. The idea is verified and quantified by advanced time-dependent DFT (TDDFT) calculations. Based on this, the hot carrier degradation can be well modeled to surprisingly cover a broad range of technologies and stress conditions, due to the multiple peaks found in the full-band resonance states, and a TCAD simulation flow is proposed. The model is experimentally validated, from classic region (130nm Planar) to advanced region (16/14nm FinFET) and extendable to GAA, covering both (100) & (110) and n & p channels with various V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</inf> /V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> bias conditions. This work provides a universal understanding and efficient simulation framework for the hot carrier reliability.