Enhanced Capacitor Voltage Balancing and DC Bias Suppression Methods for Three-Level Dual-Active-Bridge Converters
Daniel Legrand Mon‐Nzongo, Minxin Lin, Paul Gistain Ipoum‐Ngome, Tao Jin
Abstract
Three-level dual active bridge converters based on neutral point clamped legs reduce the voltage stress of power devices compared to two level. However, maintaining the capacitor voltages balanced in a wide operating range is the critical issue of this converter. To mitigate this problem, a PI feedback loop of voltage error is known, but it results in poor dynamic performances. Complementary switching states (CSS) is an alternative method that provides better results in terms of balancing time and dynamic performances. However, it provides only one balancing mode which is not suitable for various scenarios of voltage errors. To improve the performance of the CSS method, an extended CSS approach is proposed in this article. It extends the balancing modes and quantifies the voltage regulation for each mode. Then it selects the modes appropriately to keep the same balancing ability for severe voltage imbalance while realizing a lower capacitor voltage ripple compared to the CSS method. In addition, it significantly mitigates the negative effects of low sampling frequency by assigning balancing modes adequately. A sensor-less dc bias suppression (DBS) method is also introduced, which uses the error in the voltage regulation of four extended modes to estimate actual dc bias current. A PI control loop is adopted to adjust the duty cycle of switches to realize the DBS. Therefore, the voltage imbalance and dc bias can be eliminated simultaneously by the proposed methods. Experiment results show the improvement of proposed methods in terms of capacitor voltage ripple, dynamic results, and correct DBS.