NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact
Taehak Kim, Jae Hoon Jeong, Seungmin Woo, Jeonggyu Yang, Hyunwoo Kim, Ahyeon Nam, Changdong Lee, Jinmin Seo, Min‐Ji Kim, Siwon Ryu, Yoonju Oh, Taigon Song
Abstract
Nanosheet FETs (NSFETs) are attracting attention as promising devices that can replace FinFETs beyond the 5-nm node. Despite the importance of the devices, few studies analyze the impact of NSFETs at the block-level. In this article, we introduce NS3K, the first 3-nm NSFET standard cell library, and examine the results on a block-level scale. In addition to the overall process of designing a full library, we extended the scope of the buried power rail (BPR) to better layout designs. We showed that BPR, originally proposed to overcome power delivery problems, is also an effective solution for standard cell hegith reductions. Using BPR, we highlight that 4-track height standard cell designs have a negligible impact on power delivery and signal routing. Overall chip results show that the 3-nm NSFET outperforms the 5-nm FinFET by −27.4% in power, −25.8% in total wirelength, −8.5% in the number of cells, −47.6% in area, and 34.7% performance, respectively, owing to better device performance and interconnect scaling. However, careful device/layout designs and new interconnect structures must be applied to continue the scaling trend and maximize the advantages of 3-nm technology.