Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations
Dongyun Kam, Byeong Yong Kong, Youngjoo Lee
Abstract
Allowing the superior error-correction performance even for short-length codewords, the successive-cancellation list (SCL) decoding algorithm has allowed the polar code to be adopted in 5G New Radio standard for control channel. However, existing SCL polar decoders still suffer from long processing latency caused by a number of serialized internal operations. In this work, to solve the latency problem, we present several parallel computing solutions for the serialized operations, i.e., simplified data dependencies and two overlapped pruning operations. To realize the proposed parallel computing, we also introduce internal circuit blocks including dual read-port buffers, an on-the-fly parity checker, and overlapped processing units. The proposed SCL polar decoders are precisely designed with optimal design parameters by analyzing trade-offs between the latency reduction and area overheads. Implemented in a 65-nm CMOS technology, the proposed list-8 SCL polar decoder requires only 374 ns to handle a (1024, 512) 5G codeword, improving the decoding efficiency by 34.7% compared to the previous designs.