Dynamic Gate Delay Time Control of Si/SiC Hybrid Switch for Loss Minimization in Voltage Source Inverter
Zongjian Li, Chao Zhang, Jiajun Yu, Bo Hu, Zhixing He, Jun Wang, Z. John Shen
Abstract
The voltage source inverter (VSI) based on the Si/SiC hybrid switch (HyS) offers a better cost/performance tradeoff than the full-SiC VSI design. However, the Si/SiC hybrid VSI bears huge power losses with fixed gate turn-off delay time. In this article, a novel dynamic optimal gate turn-off delay time control method of Si/SiC HyS-based VSI is proposed to achieve the maximum efficiency over a wide load range. The optimal gate turn-off delay time is obtained by a load current-based mathematic power loss model. A 20-kHz 5-kW prototype of the single-phase constant current (CC) VSI using a 1200-V/25-A insulated gate bipolar transistor (IGBT) and a 1200-V/12.5-A SiC MOSFET is built to validate the proposed method. In comparison with the fixed gate turn-off delay time control method, the proposed method achieves 8% total power loss reduction and 0.24% conversion efficiency improvement at 1.5-kW output power.