SiGe HBTs with ${f_{T}/f_{\max}\,\sim\,375/510GHz}$ Integrated in 45nm PDSOI CMOS
John J. Pekarik, Vibhor Jain, Crystal Kenney, J. Holt, Shweta Khokale, Sudesh Saroop, Jeffrey B. Johnson, Kenneth J. Stein, V. Ontalus, Christopher Durcan, Mona Nafari, Tayel Nesheiwat, Sangameshwar Rao Saudari, Elahe Yarmoghaddam, Saloni Chaurasia, Alvin Joseph
Abstract
A 45nm BiCMOS process, based on PDSOI CMOS, with SiGe HBT NPNs having <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${f_{T}f_{\max}\,=\,375/510GHz}$</tex> is presented. The bipolars are integrated on a PDSOI wafer in an epitaxial region above the handle wafer to avoid self-heating concerns. To our knowledge, this is the first time a high performance SiGe BiCMOS process has been demonstrated on a PDSOI wafer. In addition to the HBTs, the technology features high performance NFETs with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${f_{T}f_{MAX}\,=\,265/330GHz}$</tex> and PFETs with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${f_{T}f_{MAX}\,=\,250/340GHz}$</tex> enabling flexibility in circuit design. A full-flow demonstration PDK, digital standard cell and IO cell libraries have been released for experimental circuit design work. This work, funded under the DARPA T-MUSIC program, will address future extensions to higher HBT performance and more-advanced CMOS nodes.