FPGA Implementation of Modified Lightweight 128-Bit AES Algorithm for IoT Applications
Jeyvarshni Vimalkumar, Harshitha Ramesh Babu, M. Bhaskar
Abstract
The rapidly increasing use of IoT devices necessitates a suitable encryption algorithm for data security. The widely used Advanced Encryption Standard algorithm (AES) algorithm is computationally complex, thus unsuitable for resource-constrained IoT devices. The proposed work implements optimized alternatives for the 128-bit AES algorithm stages, aiming to minimize power and memory usage. A Modified Lightweight variant of AES was developed using Verilog HDL and implemented on Artix-7 Basys-3 FPGA board. It was found that the total on-chip power required by the modified variant has been reduced by 81.92 % for encryption and 47.21 % for decryption. There is a significant decrease in the number of LUTs required with 76.84% for encryption and 53.53% for decryption, making it a suitable algorithm for IoT lightweight applications.