Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs
Aruru Sai Kumar, M. Deekshana, V. Bharath Sreenivasulu, Hari K. Somineni, D. Sudha
Abstract
According to Moore’s law, there have been numerous technological advancements that are currently being processed. The controllability of the device has improved significantly since a basic MOSFET with a single control gate was changed to one with many control gates. This study examines the DC metrics of a sub-5 nm node, junctionless gate, and vertically stacked nanowire field effect transistor (FET). In order to improve the factors I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> , I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> , switching ratio (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> /I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> ), DIBL, and Sub threshold Swing, the device is tuned and compared. Here, a variety of dielectric-permitivity (k) values and symmetric and asymmetric spacing are employed with spacers. 3D-VTCAD is the tool used to evaluate these characteristics. Therefore, a JL nanowire FET with the best design guarantees that it can be a candidate for low-power and superior linearity technology nodes in the future.