UVM methodology based functional Verification of SPI Protocol
Aman Kulkarni, S. M. Sakthivel
Abstract
Abstract The scalability and complexity nature of the integrated circuit design makes the verification process more complicated and time-consuming. Therefore, in the present modern-day SOC’s there is a strong need for verification architectures with increased reusability and easy accessibility. The UVM methodology-based verification architecture with reusable components is one of the widely accepted test bench architectures for carrying out such functional verification. This paper presents a UVM methodology based functional verification of the SPI protocol core with a dedicated architecture. First the SPI core is modeled using Verilog RTL. Then using the reusable components in UVM + System Verilog environment, the SPI core is verified under two modes such as i) SPI communication with wishbone interface and ii) SPI Master-Slave communication.