High-Density 3D Monolithically Integrated Multiple 1T1R Multi-Level-Cell for Neural Networks
Eduardo Esmanhotto, Laurent Brunet, N. Castellani, Djohan Bonnet, Thomas Dalgaty, L. Grenouillet, D. R. B. Ly, C. Cagli, C. Vizioz, N. Allouti, Fabien Laulagnet, O. Gully, N. Bernard-Henriques, M. Bocquet, G. Molas, Pascal Vivet, Damien Querlioz, J-M. Portal, Subhasish Mitra, F. Andrieu, C. Fenouillet-Béranger, E. Nowak, Elisa Vianello
Abstract
We demonstrate, for the first time, 3D monolithically integrated multiple 1T1R Resistive RAM (RRAM) structure storing up to 3.17 bits per RRAM. We study, using a 4 kb 1T1R array, the impact of the conductance relaxation after Multi-Level Cell (MLC) programming. We show that traditional storage applications may be limited to 2 bits per RRAM due to the overlap between conductance ranges after relaxation. On the other hand, our study concludes that conductance relaxation effect is negligible for Neural Network (NN), allowing the use of nine distinct conductance levels per RRAM (equivalent to 3.17 bits) with minimal inference accuracy loss.