FPGA-based burst-error performance analysis and optimization of regular and irregular SD-LDPC codes for 50G-PON and beyond
Mingwei Yang, Ziwen Pan, Ivan B. Djordjević
Abstract
We evaluate the burst-error performance of the regular low-density parity-check (LDPC) code and the irregular LDPC code that has been considered for ITU-T's 50G-PON standard via experimental measurements in FPGA. By using intra codeword interleaving and parity-check matrix rearrangement, we demonstrate that the BER performance can be improved under ∼44-ns-duration burst errors for 50-Gb/s upstream signals.
Topics & Concepts
Low-density parity-check codeInterleavingBurst errorField-programmable gate arrayParity-check matrixComputer scienceForward error correctionOpticsError detection and correctionPhysicsAlgorithmDecoding methodsComputer hardwareOperating systemOptical Network TechnologiesError Correcting Code TechniquesAdvanced Wireless Communication Techniques