Compact Modeling of Parasitic Capacitances in GAAFETs for Advanced Technology Nodes
Swapna Sarker, Abhishek Kumar, M. Ehteshamuddin, Avirup Dasgupta
Abstract
In this work, a compact model for parasitic capacitances is proposed for Gate-All-Around silicon nanosheet FET (GAAFET). For 3 stack GAAFET, all possible parasitic capacitance components are included according to the electric field lines and geometric structure of this device. Conformal mapping and Schwarz Christoffel transforms as well as elliptic integral methods are used to model the perpendicular capacitance as well as coplanar plate capacitance. We have also used fundamental capacitance modeling to calculate the corner capacitance. The validity of the proposed model is calibrated and verified with the 3D TCAD simulations. Evaluation is also done of how different device physical parameters affect the total parasitic capacitance. The results demonstrate that the proposed model is capable of accurately estimating the parasitic capacitance of the GAAFET device. The proposed model is also implemented in the BSIM-CMG framework to verify the model’s accuracy and application of it in the circuit simulation.