24.2 A 14b 1GS/s Single-Channel Pipelined ADC with A Parallel-Operation SAR Sub-Quantizer and A Dynamic-Deadzone Ring Amplifier

Abstract

Pipelined ADCs with high speed (≥1 GS/s) and high resolution (≥14b) are required for wireless communication and instrumentation applications. The conventional pipelined architecture is usually power-hungry due to the substantial use of residue amplifiers (RAs) and flash quantizers. In [1], a low-power ring amplifier (ringamp) is exploited as the RA in a 15b 1GS/s pipelined ADC, achieving excellent power efficiency (<10fJ/conv.-step) and high SNDR (>67dB). However, the ringamp requires bias tuning to track PVT variations, and the five pipelined stages with multi-bit flash are still potential power bottlenecks. [2] adopts current biasing and split MDAC to improve the PVT robustness of the ringamp and utilizes a backend time-interleaved (TI) SAR to reduce the number of stages, and thereby the RAs and flashes. However, its AC-coupling capacitor biasing scheme suffers from a tradeoff between bandwidth and noise, while the T1 mismatches need to be calibrated. Adopting a single-channel SAR sub-quantizer instead of a flash is an attractive approach to reduce power and circuit overhead [3]. Nevertheless, its serial conversion process inevitably increases the timing budget for sub-conversion (Fig. 24.2.1, top). To maintain ADC speed, the amplification time has to be reduced, leading to increased RA power. [3] utilizes a high-speed open-loop amplifier to reduce power, but the amplifier non-linearity limits the ADC SNDR. This design tradeoff becomes particularly critical when the resolution is ≥14b due to the stricter design requirement for RA. [4] amplifies the full-swing signal instead of the residue, parallelizing conversion and amplification. However, it significantly limits the ADC input swing. In this work, we present a 14b 1GS/s single-channel pipelined ADC that addresses the above challenges, thus simultaneously achieving excellent SNDR, SFDR, and power efficiency. A parallel-operation SAR sub-conversion scheme is proposed to parallelize the residue conversion and amplification, which reduces the number of stages and improves the ADC power efficiency. A low-noise dynamic deadzone ring amplifier is proposed to achieve low power and improve SNDR. The 28nm prototype ADC achieves 68.2dB SNDR and 85.8dB SFDR with a Nyquist input while only consuming 15.3mW, resulting in a Schreier FoM of 173.3dB.

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