Vertical Power Delivery for 1000 Amps Machine Learning ASICs
Houle Gan, Shuai Jiang, Sue Teng, Shin Yamamoto, Venkata Chivukula, Bill Edwards, Chee Yee Chung, Jason Chen, Mushafik Mohideen, Gregory Sizikov, Xin Li
Abstract
The recent explosive growth of machine learning (ML) applications has resulted in a surge of demand for compute performance from custom ASICs, and with the ending of Dennard scaling, power demands of such ASICs have also reached unprecedented levels. In this paper we describe a 48V to point-of-load power solution capable of delivering more than 1000 Amps of current at 0.8V for the latest ML ASICs. The solution follows a two-stage approach, with a fixed-ratio high-density high-efficiency first stage and a second stage module with very high density (1A/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , 1300W/inch <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ). The second stage module is integrated into the system board by surface mounting directly underneath the ASIC. This Vertical Power (VPWR) solution removes the "last mile" power loss found in the conventional lateral design, lowers I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> R loss by 70% for 1000 Amps load current, and enables many more other benefits for the overall system such as better signal integrity and thermal performance.