Reliability of Atomic-Layer-Deposited Gate-All-Around In<sub>2</sub>O<sub>3</sub> Nano-Ribbon Transistors with Ultra-High Drain Currents
Z. Zhang, Zehao Lin, Adam Charnas, Hongyi Dou, Zhongxia Shang, Jianyue Zhang, Mengwei Si, Haiyan Wang, M. A. Alam, P. D. Ye
Abstract
In this work, we systematically investigate the reliability of atomic-layer-deposited (ALD) gate-all-around (GAA) single-channel In <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> nano-ribbon field-effect transistors (FETs) with 5 nm HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> gate dielectric and a maximum on-state current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> ) approaching 20 mA/μm at drain voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> ) of 1.7 V. A channel length (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</inf> ) and channel width (W <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</inf> ) independent positive threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> ) shift under negative gate bias stress (NBS) and a negative V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> shift under positive gate bias stress (PBS) are observed universally in all GAA In <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> FETs, which is opposite to bias instability of the conventional Si CMOS and IGZO thin film transistors (TFTs). This unusual behavior can be simply explained by the concept of the trap neutral level (TNL) which is deeply aligned inside the In <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> conduction band and the generation of donor-and acceptor-like traps in different gate bias stress conditions. In addition, other reliability issues including stress and recovery, gate bias dependence and temperature dependence are also studied. This comprehensive reliability analysis establishes ALD In <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> as a competitive channel material of the back-end-of-line (BEOL) compatible FETs for 3D monolithic integration into next generation ICs.